Ever since its physical fabrication in 2008, the memristor has been promising in the fields of nanoelectronics, computer logic and neuromorphic computers. Taking advantage of the circuit properties of the memristor, this paper proposes memristor-based chaotic circuits. For the first time, memristor-based chaotic circuits have been derived from the canonical Chua's circuit. These circuits present opportunities for developing applications under the constraints of scalability and low power. They also provide a memristor-based framework for secure communications with chaos.

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System usability can be measured through various methods. One of the more important and widely ­employed techniques is 'usability testing', where asks, number of users, evaluators, and other factors are the main ­elements. This paper reviews usability testing together with current issues that can influence usability testing results, both negatively and positively. It also reviews web usability testing. In addition, in this paper, usability testing in the future is considered in order that improvements may be made.

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Interconnect parameters play an important role in signal propagation in VLSI systems. In this paper, we present the sensitivity analysis to parameters of typical on-chip interconnects for ramp response. The sensitivity to parameters for the threshold crossing time is also shown here. Computation of the output response of the interconnect, and the threshold crossing time formulas based on the multiple scales method are presented.

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Energy efficient data transfer is the key factor for the design of energy efficient wireless sensor network (WSN). IEEE 1451.5 standard explores the wireless communication schemes between multiple sensors and a data gathering node (DGN) emphasizing the multiple input single output (MISO) structure. Sensors participating in this MISO can be chosen selectively for more energy efficient data transfer and the selection is controlled by several parameters, which are not completely explored yet. In this paper, an energy efficient cooperative technique is proposed for a WSN where selected numbers of sensors are used to form a MISO structure wirelessly connected with a DGN. The selection of nodes is based on a selection function, which is a combination of channel gain, residual energy, inter-sensor distance in a cluster and geographical location. Data are sent by the sensors to a DGN using a multi-hop transmission. We are concentrating our design on the final hop where sensors transmit their data to the DGN. A mathematical model is developed to get the selection function.

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Traditional operating systems' architectures are primarily focused on achieving superior performance, albeit at the expense of sacrificing reliability. This approach is clearly inadequate, given our growing dependence on computer systems for essential and critical services. Reliability should thus be considered as a first-class citizen alongside functionality and performance, while designing future operating systems. The present paper summarizes the current trends and best practices employed to improve the reliability of operating systems. We also draw attention to the limitations and drawbacks of the prevalent approaches, discuss outstanding issues and propose some promising research directions, which may be explored to build highly reliable operating systems.

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A complete analysis of Terahertz (THz) wave generation and detection of Silicon Nanowire MOS Field-Effect Transistor (SNFET) is presented in this paper. Based on the developed SNFET-THz device theory, the dependence of THz detection of SNFET on bias and structure parameters are obtained and illustrated. The numerical technique to solve fluid dynamic equation groups, which govern the THz wave transport in SNFET, is also introduced. Based on the developed numerical tool, the THz generation and its instability are demonstrated and analyzed in details. From developed numerical simulation program, the evolution processes of THz plasma wave in generation and detection modes are presented.

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Three-dimensional (3D) integration of ICs provides unique opportunities to improve bandwidth, latency, and power dissipation bottlenecks of interconnects (both on- and off-chip). However, while 3D IC integration improves signal interconnection, it also presents new challenges, especially in power delivery and cooling ("thermal interconnects"). The focus of this paper is on some of the key challenges and promising technologies to address power delivery, cooling, and signaling in a 3D stack of logic ICs.

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